50. Fabless Semiconductor Design: India’s Design Linked Incentive Scheme

Structural Mechanics

The Ministry of Electronics and Information Technology (MeitY) launched the Design Linked Incentive (DLI) scheme to build a domestic, intellectual-property-rich fabless semiconductor ecosystem. The program provides financial support, design infrastructure access, and prototype testing resources to domestic startups. This assistance helps local design teams develop custom System-on-Chips (SoCs), analog integrated circuits, and RISC-V microprocessors, reducing reliance on foreign-owned silicon architectures.

[Fabless Startup (Custom RISC-V SoC Design)] 
    --> Access to MeitY India Chip Centre EDA Tools 
    --> [DLI Financial Support (Pari-Passu IP Subsidy)] 
    --> Prototype Fabrication at Overseas Foundry 
    --> Indigenous Chip Validation and Commercialization

Data-Driven Metrics

• IP Localization: The scheme has supported over 10 semiconductor design startups in developing custom chips for smart meters, IoT devices, and electric vehicles.
• Infrastructure Support: Startups receive access to electronic design automation (EDA) tools, IP cores, and computational resources through the India Chip Centre.
• Commercialization Pipeline: DLI-supported designs include low-power RISC-V microprocessors tailored for utility meters and consumer IoT devices.

Strategic Vector

MeitY should negotiate bulk licensing agreements with global silicon foundries to secure guaranteed manufacturing slots for DLI-supported startup prototypes.